1. Field of the Invention
The present invention relates in general to an instruction processing pattern generator controlling operations of an integrated circuit tester, and in particular to an instruction processor that implements subroutine parameter passing.
2. Description of Related Art
A typical "per pin" integrated circuit (IC) tester includes a separate channel for each pin of an IC device under test (DUT). A test is organized into a succession of test cycles and during each test cycle each channel carries out a test activity at the pin. A vector (a data word) supplied to each channel at the start of each test cycle indicates what the channel is to do during the test cycle. For example when a channel is to provide a test signal input to the pin, an input vector may tell it to change the state of the test signal at some particular time during the test cycle. When a channel is to sample a DUT output signal appearing at the pin to determine if it is of an expected state, the vector indicates when to sample the DUT output signal during the test cycle and indicates its expected state.
A typical per pin IC tester also includes a separate random access memory for each channel for storing all of the vectors the channel needs during the test. A central instruction processor, executing a program stored in a central instruction memory, supplies an address in common to the instruction memory and to all vector memories before the start of each test cycle. The instruction memory responds to the address by reading out a next instruction to be executed. Each vector memory responds to the address by reading out the vector stored at that address and supplying it to its corresponding tester channel at the start of a test cycle. Thus a sequence of instructions read out of the instruction memory tells the instruction processor how to generate a sequence of addresses, and that sequence of addresses causes each vector memory to read out a sequence of vectors to a corresponding tester channel.
Each vector memory may store the sequence of vectors needed for a test at sequential memory addresses. In such case each instruction read out of the instruction memory need only tell the instruction processor to increment the vector/instruction memory address for the next test cycle. However when a test requires a large number of test cycles, the number of instructions and vectors needed may exceed the capacity of the instruction and vector memories.
Fortunately most long tests involve repetitive operations in which certain vector sequences are repeated many times and each vector sequence that is to be repeated need be stored just once in vector memory. In such case a program stored in the instruction memory can be organized into a main program and a set of callable subroutines and the vectors stored in the vector memories are similarly organized into a main vector sequence and a set of subroutine sequences. During the test, as the instruction processor steps through the main program sequence, it sequentially read addresses the vectors of the main vector sequence. Whenever a repeatable subroutine sequence of vectors is needed, a CALL instruction input to the instruction processor tells it to jump to the first address of the vector sequence and of a corresponding instruction subroutine. The subroutine tells the instruction processor to sequentially address the vectors of the subroutine sequence. The last instruction of the subroutine is a RETURN instruction telling the instruction processor to return to the main program address following the address of the CALL instruction. Since each repetition of a vector sequence can be referenced by a pair of CALL and RETURN instructions in the main program, the amount of instruction and vector memory needed for a long, repetitive test is reduced.
Certain types of tests involve a long "mostly repetitive" sequence of vectors which might be completely repetitive except that one or more vectors differ on each pass of the sequence. For example when the DUT we test is a random access memory, we write data to each DUT memory address, read the data back out of that DUT address, and then compare the data written to the DUT address to the data read back out to see if they match. The operations of writing, reading and comparing are repetitive except that during each repetition of the process the DUT memory address being write and read accessed changes. In order to handle this "mostly repetitive" process using subroutines, it has been necessary to divide the process into several subroutines, each covering those portions of the process which are completely repetitive. The non-repetitive portions of the process, the generation of DUT write and read addresses, are handled by the main program. Thus several subroutines are needed to implement a long, mostly repetitive, process having an occasional non-repetitive section.
Subroutine calls have been handled using either direct or indirect addressing. In direct addressing the full starting address of a subroutine is included as an operand with the CALL instruction. Direct addressing allows the address space of the instruction memory to be freely subdivided into as many subroutines as may be needed. Dividing a long, "mostly repetitive" process into many subroutines is not a problem. However one disadvantage to direct addressing is that it requires the instruction memory to be wide enough to store a large operand with each CALL instruction. For example a 16 Mbyte instruction memory requires a 24-bit input address. Thus in a direct addressing system having a 16 Mbyte instruction memory, the instruction memory, in addition to having to store for example a 4-bit instruction opcode at each address, must also store a 24-bit operand for use as a call address.
In indirect addressing, the opcode stored with each CALL instruction only indirectly indicates the address of a subroutine being called. The instruction processor uses a decoder or lookup table to convert the operand into the actual address of the subroutine. For example, a 4-bit operand can reference up to sixteen subroutine start addresses. The advantage to indirect addressing is that it greatly reduces the size of the operand that must be stored in the instruction memory and therefore greatly reduces the width of the instruction memory.
The disadvantage to indirect addressing is that it limits the number of subroutines that can be stored and called. When we employ indirect addressing, where we can call only a limited number of subroutines, it may not be possible to break up a long "mostly repetitive" instruction sequence into several subroutines. What is needed is an instruction processor that can implement a long "mostly repetitive" sequence of instructions as a single subroutine in which non-repetitive sections of the subroutine can be altered with each pass of the subroutine.